In a dynamic random access memory (“DRAM”), data is stored as a logic high value (e.g., “1”) or logic low value (e.g., “0”) by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as a charge on the capacitor, the charge gradually leaks off and the data becomes corrupted. Therefore, a “refresh” cycle must be performed before passage of sufficient time for the data to become corrupted, to maintain the integrity of the data.
To read data from a memory array, the array is typically placed in a read mode to obtain the data currently stored in a row of memory cells. An individual datum is typically accessed through the cell address, which identifies a memory cell by its row and column in the array.
FIG. 1 illustrates a prior art DRAM circuit 100 having a first storage bit 132 and a second storage bit 126. First storage bit 132 is passed by a first PMOS transistor 130, and second storage bit 126 is passed by a second PMOS transistor 128. PMOS transistor 130 is coupled to sense amplifier 102 via bit line BL, and PMOS transistor 128 is coupled to sense amplifier 102 via bit line bar ZBL. Sense amplifier 102 includes pre-charge circuit 104, back-to-back inverter 112 and two NMOS transistors 122, 124, which have their gates tied to column selection line SL. Pre-charge circuit 104 is comprised of three NMOS transistors 106, 108, 110, which have their gates tied to equalization line EQ.
The back-to-back inverter 112 is comprised of two PMOS transistors 114, 116 and two NMOS transistors 118, 120. Both NMOS transistors 118, 120 have low threshold voltages for reasons discussed below. The gates of NMOS transistor 120 and PMOS transistor 116 are tied together and coupled to both the bit line bar ZBL and the drains of NMOS transistor 118 and PMOS transistor 114, which are also tied together. The gates of NMOS transistor 118 and PMOS transistor 114 are tied together and coupled to the bit line BL, and the drains of NMOS transistor 120 and PMOS transistor 116, which are also tied together. The sources of the PMOS transistors 114, 116 are tied together, as are the sources of the NMOS transistors 118, 120. The sources of the PMOS transistors 114, 116 are also coupled to a high voltage source VDD via line SP and PMOS transistor 134. PMOS transistor 134 has its gate connected to control line CL1. The sources of the NMOS transistors 118, 120 are coupled to ground VSS via line SN.
With reference to FIGS. 1 and 2, the reading of a “0” from the first storage bit 132 of prior art DRAM circuit 100 is now discussed. Initially at time t=0, DRAM circuit 100 is in normal operation (i.e., retaining previously stored data, but not being written to, read from or refreshed) and equalization line EQ is coupled to a logic “1” signal, When equalization line EQ is coupled to a logic “1,” the three NMOS transistors 106, 108, 110 of pre-charge circuit 104 are in the “on” state, and lines ZBL and BL are charged to the voltage of VBL, The voltage of VBL is typically half the voltage of VDD (assuming a VSS voltage of 0.0 volts). Also in this state, control line CL1 is connected to a high voltage signal, which turns PMOS transistor 134 to the “off” state resulting in VDD being disconnected from sense amplifier 112.
The read cycle begins at time t=1, when equalization line EQ is coupled to a logic “0” signal. PMOS transistor 130, which controls the first storage bit 132, is selected by transitioning line WL from a high voltage to low voltage. The transition of line WL from a high voltage to a low voltage turns PMOS transistor 130 from the “off” state to the “on” state. With PMOS transistor 130 on, the voltage of the first storage bit 132 is then coupled to bit line BL. Since bit line BL has a larger bit line capacitance than the capacitance of the capacitor of the first bit 132, the voltage of line BL is pulled down slightly.
Line SP is then coupled to VDD by having control line CL1 transition from a high voltage to a low voltage, which transitions PMOS transistor 134 from the “off” state to the “on” state. With PMOS transistor 134 on, the voltage of VDD is then connected to the gates of both PMOS transistors 114 and 116 of the back-to-back inverter 112, thereby changing the PMOS transistors 114, 116 from the “off” state to the “on” state. The turning on of PMOS transistors 114 and 116 pulls down the voltage of line BL while the voltage of line ZBL is pulled up. The pulling down of line BL and pulling up of line ZBL occurs because VDD pulls up the voltage of line ZBL via PMOS transistor 114, and VSS pulls down the voltage of line BL via NMOS transistor 120.
FIG. 2 is a diagram showing voltage versus time and illustrates certain signals of DRAM circuit 100 as they transition during the normal operating phase and the read phase. Of particular interest are the signals of lines ZBL and BL as they illustrate the slow transitioning from their initial voltage level at VBL at time t−1 to their respective voltage levels at VDD and VSS at time t=2. As illustrated in FIG. 2, the transition of both BL and ZBL from their initial voltage to their final voltages is slow, as the slopes of the lines indicate a gradual transition.
Due to the continually shrinking size of integrated circuits, the operating voltage VDD is continually being reduced, which reduces the ability of VDD to pull up ZBL. The reduced ability of VDD to pull up ZBL results in a delay in the transition of ZBL (an increase in the time between t=1 and t=2), and slowing the speed at which the circuit functions.
Some attempts to speed up the pulling up of ZBL by VDD have been made, including boosting the voltage level of VDD during the reading cycle. However, the boosting of VDD during the reading cycle increases power consumption of the DRAM circuit and does not dramatically speed up the reading time of a “0” from the storage bit. To help increase the ability of VSS to pull down the voltage on line BL, NMOS transistors 118, 120 are typically low threshold voltage transistors. Manufacturing circuits with different threshold voltages requires additional manufacturing processing, as all of the transistors of the circuit cannot be formed by the same steps. The additional manufacturing steps, such as additional photolithographic steps, drive up the time and cost of production.
Therefore, it is desirable in the art to provide an apparatus and method which overcomes the disadvantages of the prior art.